Technology Workshops
EMC Compliance
 

Circuit Board & Layout Issues for EMC Compliance

Workshop Overview

A one-day course targeted at PCB design professionals who want practical advice on how to design for EMC compliance from the start of a project. The aim is to provide attendees with a background in the common techniques used to avoid EMC problems both at the component selection and layout stages, as well as provide tips on embedded software issues that can produce “unexpected” problems if not considered.

Next course: Please contact us for further dates

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POST COURSE ADDITIONAL INFORMATION

  

An invaluable experience

Occasions to gain such detailed insight into practical design techniques are rare these days. This Technology Workshop is truly a unique opportunity to gain invaluable insight into the depth of the subject

Who should attend?

  • PCB design professionals
  • Engineers and managers with responsibility for the EMC Compliance

The programme

A one-day technical training workshop (day starts at 9.00 am and ends at 5.30 pm).

Venue

The workshop will be held at our training suite in Stanstead Abbotts, Hertfordshire.

Pricing and accompaniments

Price per delegate £395, All prices are in UK pounds Sterling and exclude VAT.

Pricing includes lunch and refreshments (please notify us of any special dietary requirements). All attendees will receive a comprehensive workbook containing the information covered during the Technology Workshop.

How do I book my place?

Please complete this online booking form.

Or for more information free phone: 00800 776776 66 or email: training@eda.co.uk

Delegate Comments

Workshop Highlights (click to expand)

- Cost implications

Fixing EMC problems at different stages of product design can have vastly different cost implications.

- De-coupling and by-pass capacitors

This topic is discusses the use of L-C filters, reservoir and de-coupling capacitors.

- Grounding techniques

The use of ground planes, copper fills and gridded (or matrix) grounds is shown.

- Tracking

Un-connected metallised areas, orthogonal routing and stub lines are discussed here.

- High-speed design

Signal integrity, low noise circuits and material dielectrics are the subject of this topic.

- Stack assignment

The importance of layer stack-up is illustrated using 4-layer and 6-layer examples.

- Transmission lines

Crosstalk, impedance and via parasitics are discussed along with examples of transmission lines.

- Termination techniques

Series, parallel, RC, Thevenin and diode termination techniques are discussed.

- Trends in embedded systems

One of the least documented areas of EMC; the effects of software are described.

- Risk Assessment

This topic is about the methods of assessing the EMC effect of design changes.

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Terms and conditions

Our training courses are governed by a specific set of terms and conditions, which cover a number of important issues like payment and cancellation. Please read these prior to attending the course. A copy of the terms and conditions are available on request.