TechWatch

Technical hints from Premier EDA Solutions Ltd.

www.eda.co.uk

Maximise route completion and speed in Situs.
Item ID	PC2006-0-02	Author	Tony Folan
Applies to	PCB: Autorouting
Created	31/08/06	Last modified	31/08/06

Here are some pointers from Altium on how best setup the Situs autorouter to maximise route completion and speed.

'0' Errors

From within AutoRoute » Start Autorouter you have the Situs routing Strategies dialog which contains the strategies and the errors, warning and hints to help improve the routing performance. It’s best if there are 0 errors, warnings and hints before commencing an autoroute.

Most of the time the errors, warnings and hints are due to minimum width constraints and SMD neckdown rules not being adequate or non existent. So the first port of call is to create a default SMD neckdown rule set to 100% for scope of ALL. If this doesn't clear some or all the errors, warnings and hints then it maybe necessary to add net or netclass specific SMD neckdown rules. On doing this you maybe required to alter the Minimum width constraint for these nets or netclasses.

Design Rules

Clearance rules are one of the most important areas to have a clean rule set for Situs to follow, as it can dramatically affect the speed and route quality. On transfer to Situs from P-CAD it is often the case due to the way P-CAD rules are expressed in regards to clearance, that excessive amounts of layer based clearance rules are created. These rules should be factorised into the least amount of rules possible. For example if there are a lot of one particular clearance dimension rule like 6mil, then it’s a good idea to make this the ALL scope clearance. Duplicate clearance dimension rules on adjacent layers like for example 10mil on top layer for via to via which occurs on all layers can be factorised to just via to via only scope.

Try to factorise the Widths rules in much the same way as the clearance rules, so apply specific widths to certain nets, netclasses and layers then use the ALL scope for everything else.

Make sure a via style rule has been setup for the board that works, i.e. in the case of a BGA, fan-out and escape can occur with the via, track and clearance combination. Via styles can only be set on a net or netclass basis. Make sure multiple ALL scope via style rules don't exist, as these well just slow things down.

Fanout test

Make sure that fan-out is possible by running fan-out on all or on specific components like BGA’s. This is a quick and easy way to see if the correct via size is being used or if the fan-out is even possible.

Strategies

For strategies, if the board is a multilayer design then generally the Default Multi Layer Board strategy should do the job in most cases. For 2 layer boards then use the Default 2 Layer Board strategy. Strategies can be modified to reduce or increase via count which can affect the routing time and completion percentage. Running additional clean up passes can help improve the quality of the routed board in regards to lowering the contentions and possibly increasing the completion percentage. It’s also possible to create a custom strategy using a main pass called Global Optimised Main. This works differently to the regular main pass, and because of this can produce vastly different results, sometimes better.

Blind and Buried Vias

If possible blind and buried via’s can be used to increase the route completion. Make sure drill pairs have been setup in the Drill pair manager before trying this.

Pre-routes

Pre-routes are supported on translation to Situs and not ripped up if the lock all pre-routes option is ticked, however some pre-routes can cause issues for Situs. Pre-routes that are only dog legs with no via are of most concern. If pre-routes are to be placed then they should be point-to-point routes or if there dog legs, then they should end with a via or pad (even smd). With Situs' strong capabilities of component fan-out, in nearly all cases it’s not necessary to pre-routes dog legs.