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This TechWatch is based on the third layer and final part of my Design Reuse with Altium Designer presentation from our user conference on the 31st October 2006. The files for this and all of the other TechWatch's in the Design Reuse series can be downloaded here (451kb).  Once downloaded this TechWatch we will be working with files from the C:\Design Reuse TechWatch Files\Core Component files folder.

Design Reuse methodologies can be implemented as a number of “layers”

Layer 1: Features that allow fast and “intelligent” cloning of localised circuitry.

Layer 2: Reusing entire schematic sheets and multi-channel design techniques.

Layer 3: Creation of re-usable, pre-verified, core “components” stored in libraries.

Layer 2:

Summary

In Layer 2 we looked to reuse much larger elements of circuitry or entire schematic sheets. When using a pre-existing schematic sheet we need to be aware existing annotations and sheet numbers. We’ve looked at Multi-Channel Design to duplicate the same section of a design multiple times. It is worth noting that the techniques we used here work just as well when updating existing schematics. Then lastly we looked at Parametrical Hierarchical Design. This is similar to Multi-Channel Design but allows us to assign different values to each channel.

Layer 3:

Creating a Core Component

With Altium Designer, we have the ability to encapsulate an entire FPGA circuit into a pre-verified block. These self-contained blocks are called core components and offer the advantage of design reuse and design security. The output of a Core project behaves in a similar fashion to a library component in that it becomes an elemental unit that is used as a component in larger designs.

We are going to take a schematic version of a clock divider and create a core component from it. To create a core component we firstly need to create a core project using File ›› New ›› Project ›› Core Project. Save the project as MyCore.PrjCor to the Core Component files folder using the File ›› Save Project As... command.

We then need to add our captured design into the project. In this case our Clock Divider. Add the Clock_divider.SchDoc to our MyCore.PrjCor by right clicking on it in the Projects panel ›› Add Existing to Project. Then open it.

Under Project ›› Project Options ›› Options, we need to ensure that ‘Include models in published archive’ is checked. This will ensure that the generated EDIF files are published within one zip file.

Using the FPGA Preferences (Synthesis) (Tools ›› FPGA Synthesis) we now setup set up the user pre-synthesized model folder i.e. where we shall create the synthesised model. There is a MyCores folder in our Core Component files folder for us to use.

We now need to setup the configurations and constraint files to target the devices we want our core component to be used on. If we wished we could setup multiple configurations to allow the core to be used on different FPGA Devices.
Add a new Constraint File to the project (File ›› New Constraint file). Using the Design ›› Add/Modify Constraint ›› Part and select the XC2S300E-6PQ208C device.

Save the Constraint file as MyCoreXilinx.Constraint. Open the Configuration Manager (Project ›› Configuration Manager) and add a configuration and call it MyCoreXilinx and check the box to add our constraint file.

Now we need to synthesise our core component. This generates VHDL files from any schematics we may have and produces EDIF files of our core. To do this switch back to our Clock_divider.SchDoc and use the command Design » Synthesize All Configurations. We can now publish our core project, which will zip up all of the EDIF files and place them in our \My Cores\ folder. Use the command Design » Publish.

Generating the schematic symbol for our core.

We have now generated all of the EDIF files for our core component, which means we can create a schematic symbol to represent it.
Use the command Design ›› Generate Symbol, this will create a new schematic library file and produce a symbol from the schematic. Click Yes to new library and Options dialog boxes. Save the new library and symbol to a library (MyCore.SchLib in the working folder). Select Add Existing to Project. Add the library.

This FPGA component may now be used multiple times within this or across many FPGA projects.

This is the last Design Reuse techwatch in the series, return to the previous TechWatch.