National Electronics Week 2009
Unleash your creativity
 

UK Design Innovation Conference

The UK Design Innovation Conference is an exciting new addition to National Electronics Week - the UK’s leading electronics exhibition.

Open to electronics design professionals, engineering managers and technicians, the UK Design Innovation Conference will provide an unsurpassed platform for learning, discussion and networking. “The needs of the UK electronics design community are broad, deep and wide.” says Phil Mayo, Managing Director of Premier, “Irrespective of the current economic climate, design professionals need a national event where they can ‘toe dip’ into new technology developments, design techniques, industry comment and such like. The UK Design Innovation Conference provides the ideal vehicle for this.”

The conference provides a comprehensive programme of technical sessions loosely organised into three tracks for each of the three days of the exhibition. These tracks cover subjects associated with Advanced PCB Technologies, Intermediate PCB Design Techniques and Design Considerations beyond the PCB. Industry experts have been invited to contribute non-commercial materials targeted at electronics design professionals in order to maximise the learning experience for each session.

Further information:

Conference Agenda (click to expand links)

Day One - Tues, 16th June

10:45 - 11:05 Keynote Speech - Richard Noble

Richard Noble, the driving force behind British World Land Speed racing for over 25 years, welcomes you to National Electronics Week. Richard is Director of the BLOODHOUND Project. "This is an iconic engineering and education adventure for the 21st century that is pushing technology to its limit. We aim to inspire the next generation of engineers and scientists by designing and building our incredible car capable of 1000 mph!"
 

11:15 - 12:40 High-speed PCB design for Signal Integrity and EMC – an integrated approach - Robert Easson, Analytical Edge

Synopsis: This seminar shows how thinking in terms of current and frequency (bandwidth), rather than just voltage and time, can help designers to understand key aspects of SI and EMI, including power delivery, signal transmission, coupling, and radiation.
Bio: Robert Easson has many years of experience in design engineering, technology and engineering management gained with companies engaged in microwave, RF and telecommunications engineering. He set up Analytical Edge, an independent consultancy, which for the last ten years has specialised in developing courses in high-speed PCB design and EMC and delivering them to engineers and PCB designers throughout western Europe and North America. Robert has a BSc in physics and a PhD in engineering, both from the University of Glasgow, and is qualified as a Chartered Engineer and MIET.
 

14:00 - 15:00 PCB transmission line losses - what designers need to know about fabrication - Neil Chamberlain, Polar Instruments

Synopsis: An introduction to the increasing requirement for the modeling and measurement of high speed pcb transmission lines operating at frequencies where trace attenuation requires control and management. Includes high speed transmission line history on PCBs and some of the challenges facing designers and fabricators.
Bio: Neil Chamberlain is European Sales Manager of Polar Instruments Ltd. He began his career at IBM in the early 1990’s where he was a manufacturing engineer responsible for special projects within the Network systems division. He then moved Procurement where he was responsible for PCBA purchasing from both European and South East Asian Sub-Contract Manufactures. Neil joined Polar in 2000 where he was responsible UK sales. He became European Sales manager at Polar during 2005 as the market for Signal Integrity Simulation and controlled impedance test became a major section of Polar’s product range, Neil also speaks regularly at EIPC and ICT events and contributes to IPC High Speed High Frequency standards development activities.
 

15:00 - 16:30 EM simulations for EDA applications - Mohan Jayawardene, CST

Synopsis: In the ongoing race for reduced design cycles, costs and faster times to market, design engineers working on the signal integrity of systems containing cables, multilayer PCBs, and passive components, can benefit from streamlining their workflow using EM simulations. Through this highly integrated workflow, SI and EMC issues can be addressed early in the design process, reducing the number of expensive cut and try iterations. In this talk the authors present a compilation of application oriented examples where Electromagnetic Field simulation using CST MICROWAVE STUDIO® (CST MWS) can be used to accurately simulate and predict SI and EMC issues. One such example is simulating the power supply noise in multilayered IC packages. As microprocessor clock frequencies increase and their ASIC power supply voltages decrease to 2.0V and below, the power distribution system of IC packages becomes an increasingly important design challenge. A number of vias are used both to connect power planes at multiple locations to each other, and also multiple ground planes to each other. An important design issue is how to determine the number of power and ground planes, and the number and the locations of power and ground vias, for a given power supply noise margin. Accurate characterization of power supply noise is simulated using CST MWS by predicting various electromagnetic interactions in the package and validated using measurements.
Bio: Mohan Jayawardene completed his PhD at Loughborough University and continued to work at the Centre for Mobile Communications Research (CMCR) as a Senior Research Engineer, focusing his work on antenna designs for the telecommunication, aerospace and defense markets. Mohan joined CST in October 2005, and currently works as the Technical Sales Manager for CST UK Ltd based in Nottingham.
 

Day Two - Weds, 17th June

10:30 - 12:40 Panel discussion - "Are there too many constraints on modern electronics design?"

All visitors are invited to attend an open discussion session. The theme for the debate will be “Are there too many constraints on modern electronics design?” and will bring together the views of UK electronics industry champions in a lively discussion designed to focus thought and provoke action.
Panellists:
    - Harry Tee, Chairman, Electronics Leadership Council (chair)
    - Huvin Thompson, VP of Instrumentation & Analytical, ABB
    - Nick Kings, Hardware Engineering Manager, Ericsson
    - David Brooks, ex-VP Systems & Architecture, Snell & Wilcox
    - Richard Hollinshead, Director of Engineering, Meridian Audio
    - Steven Kear, Director, AND Technology
 

14:00 - 15:00 The EMC Techniques That Should Now be Used On (Almost) All PCB Designs Part 1 - Keith Armstrong, Cherry Clough

Synopsis: The first of two 1-hour sessions, this describes well-proven EMC techniques that should be applied at PCB level to...
    - reduce development time and cost
    - reduce unit manufacturing costs
    - speed time-to-market
    - help comply with the EMC Directive by reducing the number of design iterations required to pass EMC tests
    - reduce warranty costs by improving product reliability.
Bio: Keith graduated from Imperial College, London, in 1972 with an Honours Degree in Electrical Engineering, has been a member of the IEE (now called the IET) since 1977, a UK Chartered Engineer since 1978, and a Group 1 European Engineer since 1988. After working for a number of manufacturers as an electronic designer and later as project manager and design department manager, Keith started Cherry Clough Consultants in 1990 to help companies reduce costs, timescales and warranty costs whilst also complying with the EMC Directive and other EMC regulations world-wide.
Keith has presented many papers, demonstrations, and training courses on EMC, and on EMC for Functional Safety, worldwide, and has also written very many articles on these topics over the last 18 years. He is President of the EMC Industries Association (EMCIA), which is based in the UK, and chairs the IET’s Working Group on “EMC and Functional Safety”. He is also the UK’s authorized representative on the IEC teams working on: IEC 61000-1-2 (EMC & Functional Safety, MT15), and IEC 60601-1-2 (EMC for Medical Devices, MT23).
 

15:30 - 16:30 The EMC Techniques That Should Now be Used On (Almost) All PCB Designs Part 2 - Keith Armstrong, Cherry Clough

Synopsis: The second of two 1-hour sessions, this describes well-proven EMC techniques that should be applied at PCB level to...
    - reduce development time and cost
    - reduce unit manufacturing costs
    - speed time-to-market
    - help comply with the EMC Directive by reducing the number of design iterations required to pass EMC tests
    - reduce warranty costs by improving product reliability.

 

Day Three - Thurs, 18th June

10:30 - 11:30 Thermal Management at the PCB Level - Jeff Punch Stokes Research Institute

Synopsis: Thermal management has become a critical aspect in the design of contemporary electronic systems. Power dissipation levels have increased due to increased functionality and greater degrees of integration, and careful thermal design is imperative in order to meet today’s stringent requirements for reliability.
The objective of this talk is twofold: to review contemporary thermal roadmaps for a range of product categories; and to cover the fundamentals of heat transfer which underpin thermal design practice. Attendees will gain an understanding of current and future challenges in thermal management, and fundamental tools for working on thermal design at PCB- and system-level.
Bio: Dr. Jeff Punch is currently Director of Micro-Mechanical Engineering at the Stokes Research Institute, University of Limerick (UL), collaborating with the Institute’s partners and clients on a range of research programmes. At present, he has wide-ranging research interests in the analysis of micro-scale mechanical engineering phenomena within the application arenas of electronic and micro-electromechanical systems – with particular emphasis on thermal management and failure physics. He has authored or coauthored over 35 refereed publications and five patents, and has presented more than 50 invited talks on aspects of the thermal management and reliability of electronic systems at venues in Europe, USA, the Middle East, India and Asia-Pacific. Education: B.Eng. in Mechanical Engineering, and a Ph.D. from UL.
 

11:40 - 12:40 The benefits of Boundary Scan for hardware development - Nick Hardy, XJTAG

Synopsis: Increasing board and device complexity, coupled with the need to develop products quickly, means more pressure for hardware engineers. With JTAG (Joint Test Action Group) Boundary Scan now implemented in so many devices, it becomes the obvious tool to help engineers develop and manufacture products more quickly. This session gives an overview of how to get the maximum benefit from using that small JTAG connector on you boards.
Bio: A hardware engineer by training, Nick has worked in manufacturing, design and hardware test for eight years. At XJTAG, he has helped develop test systems and strategies for UK and European clients, from small start-up companies to multinationals. At a previous company he managed hardware design and sourcing, so understands (from experience!) that engineers need time and proper test tools to produce good quality products.
 

12:40 - 13:30 Challenges of PCB design using FPGAs - Michael Buckley, Lattice Semiconductors

Synopsis and speaker bio to follow
 

14:30 - 15:00 Intermediate PCB design techniques - Alan Johnson, Premier EDA Solutions

Synopsis to follow
Bio: During an apprenticeship with GEC Power Engineering, Alan obtained a HNC from North Staffordshire Polytechnic. Following a move to Michelin Tyres (R&D Dept), Alan became involved in designing equipment for computer controlled vehicles used for tyre testing. Alan then moved into the teaching profession as College Lecturer at Stafford and subsequently gained a UCertEd (Post Compulsory teaching qualification) from the University of Wolverhampton.
Training Manager at Premier was Alan's next appointment, where he became involved with the IPC Designers Council, becoming a member of their Education Committee and eventually Vice Chairman Executive Board of the Designers Council. During this time Alan became a qualified designer via the IPC Designers Certification Programme up to advanced level (CID+) and currently he is the only qualified tutor in the UK & Ireland for the advanced level.