Integrating programmable devices into the physical design

Large scale programmable devices are increasingly finding their way into mainstream electronic development. They bring significant benefits to the design process, allowing functional complexity to be moved from hardwired devices into the programmable realm. Today it is crucial for design productivity that these devices be seamlessly integrated into the physical design process.

In Altium Designer our proven strength in board-level system design has been integrated at the platform level with support for programmable design within an FPGA environment.

Altium Designer solves the problems of working with large-scale programmable devices by providing seamless linking of FPGA design projects with the board design that incorporates them.

The extensive use of FPGAs within a system design has some compelling benefits, not the least of which is rapid chip development cycles. But time saved in the development of the FPGA circuitry does not automatically translate to faster time to market for the end product.

One of the features of FPGAs is that the pin configuration of the devices is configurable. As well as defining the function of each pin, you can select from a wide range of electrical I/O characteristics. While this provides immense design freedom, it also leads to significant problems with incorporating these devices onto a PCB. This can negate much of the time saved in the FPGA development stage.

Altium Designer solves the problems of working with large-scale programmable devices by providing seamless linking of FPGA design projects with the board design that incorporates them. This allows you to gain the full benefits that programmable devices have to offer, and opens the door to a new way of approaching electronic product development.

Altium Designer facilitates complete FPGA-PCB co-design and enables rapid development of FPGA-based applications.

Altium Designer provides a unified environment for the design of both the internal configuration of programmable devices and the PCB platform that they reside on. This facilitates complete FPGA-PCB co-design and enables rapid development of FPGA-based applications.

Because the projects are linked at the design level, you can begin the physical design process using a default FPGA configuration while the FPGA is still in development. As FPGA development progresses, updated pin and I/O assignments can be transferred to the board design project. The physical schematic representation of the FPGA device is automatically updated to reflect the updated I/O definitions, keeping existing connectivity intact. These changes can then be flowed on to the PCB.

Altium Designer abstracts FPGA design from the physical constraints used to drive the FPGA place and route process. This allows you to maintain multiple FPGA configurations within a single FPGA project. For example, you have one configuration targeting your FPGA development environment and another for your production board design. This lets you seamlessly move between development or production builds of the FPGA and further facilitates concurrent design of the FPGA and the physical platform.

Managing I/O synchronisation

Programmable devices such as FPGAs bring particular challenges to the board design process. Typically these devices have a large number of pins whose I/O characteristics and functions are not fixed, but determined by the application programmed into them. Traditionally crucial I/O pins will be fixed by the FPGA designer, with the FPGA place and route tools free to assign the remaining pins as necessary.

The result at the board level is a pin configuration that is generally far from optimal for PCB routing, and the task of propagating I/O characteristics for processes such as signal integrity analysis becomes time consuming and error prone. Because Altium Designer unifies the process of FPGA and PCB design, it fully supports I/O synchronisation between the PCB and FPGA projects. This allows you to forward and back annotate pin assignment changes and automatically propagate I/O characteristics for signal integrity simulation and differential pair management.

Achieve optimal routing solutions with FPGAs

As you deploy FPGAs within the PCB layout, you can define sets of pins that can be interchanged at the board level. From within the PCB design you can manually swap pins to improve routing, or let Altium Designer automatically optimize the connection lines for easier board routing. With a few mouse clicks you can then propagate pin changes back to the FPGA project, and rerun the FPGA place and route process with the new constraints. This allows you to rapidly iterate through PCB and FPGA routing options to arrive at an optimal system-level design solution.

The unification within Altium Designer of the programmable and physical elements of an electronic product allows you to take full advantage of the benefits that large capacity FPGAs offer. Altium Designer allows you to effectively manage the complexity FPGAs introduce at the board level, and removes the barriers to their widespread adoption with mainstream design.

With Altium Designer, software can be easily changed and updated throughout the development cycle and can be debugged interactively on the target execution platform.

Many of today’s high-density FPGA devices come in gridded packaging such as BGAs. It is often extremely difficult or impossible to physically probe pins on these devices to determine signal status during system development. This can make physical debugging of the circuit a difficult challenge.

Altium Designer leverages the JTAG capabilities of FPGAs to allow you to dynamically investigate the status of any pins on the device without the need for physical access to the pins. JTAG boundary scan allows for transparent monitoring of the signal status on the device. When your Altium Designer system is connected to a suitable development board, such as Altium’s device-independent NanoBoard, or your JTAG-equipped prototype or production board, the in-built, real-time JTAG Viewer allows you to easily view the state of all the pins on any JTAG supported component. This forms part of Altium Designer’s interactive FPGA development methodology – LiveDesign.

The JTAG Viewer presents you with a footprint and symbol view of the target device. You can manually capture a snapshot of the pin status of the device, or have the display update dynamically as the circuit operates. You can hide the display of unused pins, and select any single or group of nets within your design to focus on. This allows you to easily monitor the status of just the pins you are interested in.

Pin status can also be dynamically reflected and displayed on the source schematics for your project, and the PCB layout. This allows you to easily trace signals throughout the entire design.

With Altium Designer, you can monitor the status of critical lines in real-time as you exercise the circuit to determine correct state changes, and easily see problems such as stuck signal lines. This ability to easily view the status of the physical pins of an FPGA, or indeed any JTAG device supported by the system, provides a valuable aid in debugging your design at the physical level when working with high pin-count JTAG-enabled devices such as FPGAs.

Go back to the Altium Designer 6.0 Product Overview or select a process from above.